Follow instruction execution, pipelines, caches, and virtual memory.

1. Instruction Cycle

   Follow register and memory transfers as a simple CPU fetches, decodes, and executes instructions.

2. Pipelines and Hazards

   Step through a five-stage pipeline, data and control hazards, and forwarding.

3. Cache Mapping

   Split addresses into tag, index, and offset; compare direct-mapped, set-associative, and fully associative caches.

4. Virtual Memory and the TLB

   Translate virtual addresses through the TLB and page table, and observe page faults.

5. Branch Prediction

   Compare always-taken, one-bit, and two-bit predictors on branch patterns such as loops.