A CPU repeatedly fetches an instruction from memory, decodes its operation, and executes it. Follow the transfers between registers and memory one step at a time.
A simple-CPU simulator for fetch, decode, and execute cycles
1. Choose a program
2. Execute step by step
Orange arrows show the transfer performed in this step; orange boxes show changed values. The ▶ marker in memory indicates the next instruction selected by PC.
Every instruction begins with fetch
Copy PC into MAR, read that address into MDR, then copy the instruction to IR and increment PC. In this model those fetch steps are shared by every instruction. Execution differs by opcode. A jump changes PC during execution, altering the next fetch address and enabling loops.
Why memory access is expensive
Each instruction needs a fetch; LOAD, ADD, and STORE also access operand memory in this model. Registers are fast, while main-memory access can take many CPU cycles. A cache reduces repeated memory access, and a Pipeline overlaps the work of multiple instructions.
Instructions in this CPU
LOAD a ACC ← M[a], ADD a ACC ← ACC + M[a], SUB a ACC ← ACC − M[a], STORE a M[a] ← ACC, JZ a sets PC ← a if ACC is zero; JMP a PC ← a, HALT stops execution. Keeping arithmetic results in ACC makes this an accumulator architecture. General-purpose CPUs typically provide multiple general-purpose registers.