Digital Logic

DRAM and NAND Flash

Update one item sends the same request to DRAM and NAND. DRAM overwrites the existing cell; NAND writes a new copy into a free page. When NAND runs low on free pages, observe valid data being moved and the old block being erased.

A simulation comparing DRAM and NAND updates and their latencies

DRAM read/write
~50 ns
NAND page read
~50 µs
NAND page program
~500 µs
NAND block erase
~2 ms

Bar lengths show latency differences on a logarithmic scale.

DRAM · capacitor cellsElapsed time 0 µs

DRAM can write a new value directly into the selected cell. A blue outline marks the row being refreshed.

NAND flash · blocks and pagesElapsed time 0 µs, pending 0

Green pages hold current data. A crossed-out page holds an obsolete copy; a dashed outline marks a free page.

At 1× speed, each real microsecond is expanded to 2 ms on screen. DRAM charge leakage and refresh use a separate illustrative timescale.

L0, L1, and so on identify logical data items. Updating an item preserves its ID but changes its physical NAND page.

NAND flash is named after its cell arrangement

NAND flash connects cells in series, resembling the transistor arrangement in a NAND gate. It does not store data in a NAND logic gate itself. NAND reads and programs pages, but erases an entire block containing multiple pages.

DRAM needs periodic charge refresh

DRAM represents bits as charge in tiny capacitors. It can overwrite a cell directly; this example assumes approximately 50 ns per write.

Capacitor charge leaks over time, so DRAM periodically reads and restores cell values. This is refresh. When power is removed and charge cannot be replenished, the stored data is lost.

NAND cannot directly overwrite an occupied page

NAND stores charge in an insulated structure and retains data without power. Updating it is slower than DRAM: this example assumes about 500 µs per page program.

An occupied NAND page cannot simply be overwritten. Updated data is written to a free page, and the old copy is marked invalid.

When free pages run low, valid data is moved to another block and the original block is erased. This is garbage collection. It is necessary because individual pages cannot be erased independently.

SSD and eMMC controllers use a flash translation layer (FTL) to map logical addresses to physical locations. They also manage garbage collection and spread writes across blocks to distribute wear, a technique called wear leveling.