A pipeline divides instruction processing into stages. As one instruction advances, another enters, overlapping their work like washing one load while drying another. Dependencies and branches can interrupt this flow.
A five-stage pipeline simulator showing overlapping instructions and hazard stalls
1. Choose an instruction sequence and forwarding mode
2. Advance one clock at a time
Rows are instructions and columns are clock cycles. Toggle forwarding on the same sequence and compare stalls and total clocks.
Data hazards and forwarding
add r1, r2, r3 followed immediately by sub r4, r1, r5 creates a dependency: sub needs r1 before add reaches WB. Without forwarding, sub waits in ID for the register write. Forwarding sends add's EX result directly to sub's EX input, avoiding that wait in this model.
A load-use dependency still needs one stall
lw obtains its value only in MEM. An immediately dependent instruction needs it in EX too soon, so even forwarding leaves a one-cycle stall in this pipeline. Scheduling an independent instruction between them can hide the delay.
Branches make the next fetch uncertain
This model resolves a branch in EX, by which time two following instructions have been fetched. If taken, they are discarded and fetching restarts at the target. CPUs use Branch Prediction to guess the outcome early.