Programs use their own virtual address space. The CPU splits an address into page number and offset, finds the physical frame through translation, and forms the physical address. A TLB caches recent translations to speed up this process.

A simulator of virtual-to-physical address translation using a TLB and page table

1. Choose virtual addresses (256-byte pages, 8 virtual pages, 4 physical frames)

TLB (4 recent translations)

Page table

Physical memory

Steps split the address, check the TLB, consult the page table if needed, and calculate the physical address. Initially only pages 0 and 3 are resident.

Page numberAddress ÷ 256

OffsetAddress % 256

Physical addressFrame × 256 + offset

TLB hit rateOften very high

Why use virtual memory?

Separate address spaces isolate programs. Demand paging also lets a program run with only some of its pages resident. This model treats a nonresident page as a page fault and fetches it from disk into a frame. When memory is full, the victim is chosen by a page replacement algorithm. This example uses FIFO: evict the earliest loaded page.

Without a TLB, translation adds memory accesses

In this simplified single-level model, the page table is in memory, so an access needs a page-table read followed by a data access. A TLB caches translations inside the CPU and avoids the page-table read on a hit. Real multi-level tables can require additional accesses.

Exercise: effective access time

Let TLB lookup time be t, memory access time m, and hit rate h. In this serial single-level model, a hit costs t + m and a miss t + 2m, excluding page faults. Effective access time is h(t + m) + (1 − h)(t + 2m). With t = 1 ns, m = 100 ns, h = 0.98, the result is 103 ns.